1. Field of the Invention
The present invention relates to a system for performing verification and testing of electrical circuits.
2. Art Background
The use of computer aided design (CAD) tools to design and physically test the designed electrical circuits have become quite popular. Using these tools, a circuit designer can develop a circuit, simulate the operation of the circuit to verify the circuit operation and subsequently generate the information necessary for a circuit testing apparatus to test the fabricated circuit.
Before fabrication of the electrical circuit, it is desirable to perform a verification of the operation of the system in order to determine whether the system designed would operate as intended. A variety of tools which perform a verification of an electrical circuit design often referred to as "switched level tools" presently exist, such as SPICE, provided by the University of California, Berkeley; MOTIVE, provided by Quad Design Technology Inc., Camarillo, Calif.; VERILOG, provided by Cadence, Inc., San Jose, Calif. and LSIM, provided by LSI Logic, Milpitas, Calif.
Typically, a simulation will perform a functional analysis and a timing analysis on the circuit. A functional analysis verifies that the logic of the circuit operates as intended. Timing verification determines that the components of the circuit operate within time constraints and are compatible with interconnected components. For example, as shown in FIG. 1a, the circuit may consist of one or more components 10, 15, 20 which communicate, for example, via bus 25, 30, with each other or input or output information.
The advances in circuit technology have rendered many of these tools inefficient and difficult to use. Circuits today are processing signals faster and faster. Signals are communicated along signal lines at very high speeds. However, with high speed signals, the lines interconnecting components can no longer be simply configured by RC modeling to simulate loading, but operate with the characteristics of transmission lines which have varying effects on the circuit timing and therefore must be modeled in order to accurately perform verification. Many logic verification programs are digital in nature and do not have the capability to accurately model a complex analog transmission line.
To address this problem existing tools have been modified to verify both the digital components and analog transmission lines. An example is MBSIM product provided by LSI Logic, Inc., or Verilog PLI provided by Verilog. In these mixed mode or "switched level" tools, a logical or digital verification is sequentially performed on a chip and carried through the analog environment of the transmission line to the input of the next chip at which time a digital or logical simulation is performed. This simulation requires a significant amount of time to perform as the digital and analog testing is serial in nature. Furthermore, the simulation requires a significant amount of memory in order to maintain the various states of the different components in the circuit.
Furthermore, the margins which specify the range of time values permitted for each signal have become narrower and thus less forgiving due to the increase in signal speeds. Therefore, the need to accurately and precisely verify a circuits' timing is even more important.
Typically each chip manufacturer has developed a set of tools to assist in the verification of designs using their components. However, compatibility among the different tools by different manufacturers is minimal at best. Previously, this was not a problem because a circuit would only include components provided by a single manufacturer and that, manufacturer's design tools would be utilized. However, today it is not at all uncommon to develop a circuit which includes components from a variety of manufacturers. To overcome incompatibility problems, a circuit designer may develop a behavior model of a component which is not compatible with the tools that are in use. However, these behavior models often do not precisely emulate the component, resulting in unforeseen results when the component is subsequently tested.
The overhead of a prior art system which attempts to perform both timing and functional testing is quite significant. The overhead is incurred due to the sequential nature of the verification operation. Functional and timing verification is performed on each component and interconnect of the circuit. This process is quite slow and requires a significant amount of memory to maintain the information for each component during verification of the circuit. This is better explained with reference to FIGS. 1b and 1c.
FIG. 1b illustrates portions of two components 35, 40 interconnected via a signal line 45 and system clock line 50. Referring to FIG. 1c, in order to verify proper timing between components 35, 40 the signal output by Chip 1 35 must be stable at the input of Chip 2 40 prior to the setup (and hold) time specified for Chip 2 40 and the propagation delay through buffer B2 55. The margin 60 identifies the amount of time between when the output signal is stable at the input of Chip 2 40 and when the output signal is latched by Chip 2 40. To determine the margin, propagation delay through the flip flop 60 and buffer 65 must be determined, as well as the delay caused by transmission line T1 70. Furthermore, the setup and hold time for the input to Chip 2 40 as well as the propagation delay through the buffer B2 55 is factored in.